Non-volatile memory is a type of memory that can retain data and information even when power is not applied. An example of non-volatile memory that is being used in a variety of applications such as cellular phones, digital audio players, and digital cameras, is “flash memory.” Flash memory is a form of electrically erasable programmable memory where data can be written to or erased in blocks of memory. The cell density of flash memory devices can be very high, often as high as conventional dynamic random access memory (DRAM) cells. Flash memory devices also have relatively fast data access times and require low operating power. With improvements in programming capabilities and the continually increasing demand for persistent and low-power memory devices, the application of flash memory in many other areas has expanded very rapidly.
The storage capacity of a flash memory array can be increased by storing multiple bits of data in each flash memory cell. This can be accomplished by storing multiple levels of charge on the floating gate of each cell. These memory devices are commonly referred to as multi-bit flash memory cells or multi-level cells (“MLC”), In an MLC, multiple bits of binary data corresponding to distinct threshold voltage levels defined over respective voltage ranges are stored within a single cell. Each distinct threshold voltage level corresponds to a respective combination of data bits. Specifically, the number N of bits requires 2N distinct threshold voltage levels. The development of MLC NAND flash has dramatically increased the storage capacity of flash memory devices.
A typical flash memory device includes a memory array containing a large number of flash memory cells arranged in rows and columns. Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic flash memory cell configuration of each is arranged. The NAND flash architecture enables faster write and erase operations by programming blocks of data, and is conventionally ideal for low-cost, high-density, high-speed program/erase applications. The individual memory cells of the NOR flash architecture are connected in parallel, which enables the device to achieve random access. NOR flash memory is ideal for lower-density, high-speed read-only applications such as code-storage applications that do not need to be frequently updated. The NOR flash memory conventionally has a faster access time and are more robust than NAND flash, but require longer erasing and programming times.
Devices that support the NAND flash memory as an alternative to or an addition to NOR flash memory have made NAND flash a viable alternative for a broader array of applications. Greater demand for high data storage capacity and performance requirements particularly for embedded applications such as cellular phones, handheld computers and other portable devices have increased significantly. However, due to the high reliability requirement for storing program data such as operating system (“OS”) data or boot code, the conventional approach has been to store OS data in a highly reliable location. An integrated memory device incorporating the two types of flash memory combines the robustness of the NOR flash architecture for storing high reliability data and the large capacity of the NAND flash architecture for storing general user data that require less reliable storage. Therefore, memory architectures that combine NOR with NAND for data storage, or that use NAND as the primary flash memory in combination with low power DRAM in which the program code can be stored and accessed are highly desired.
The NAND/NOR flash devices have generally work well for a number of applications to increase the storage capacity of these devices. In the NAND/NOR devices, the NAND architecture is used to store user-type data, and the NOR architecture is used to store operating system-type data. However, as portable devices continue to decrease in size, and the demand for smaller memory devices grows, reductions in the overall size of the memory device are limited due to the bulky size of the NOR flash memory. Although, it is more desirable to utilize a single architecture, namely the MLC NAND architecture, to store both the user data and the high reliability data, the MLC NAND architecture may not meet the reliability requirements of many applications. While it is more economical to have all data types on one MLC NAND system, a highly reliable system is necessary for storing high reliability data, such as OS software data and code.
One possible solution in the prior art has been to utilize MLCs for storing user data and single-level memory cells for storing high reliability data in a single SLC NAND device. While MLCs have a higher storage capacity due to each cell being able to store more charge states, SLCs may be programmed and read at a faster rate since only one bit is stored in each cell. Therefore, since only one threshold level is necessary to read the single bit, SLCs require less precision and the single bit can be stored more reliably. Due to the large capacity of the MLC NAND device and the need for an advanced file management system, the allocation of SLC-type storage and the MLC-type storage are typically permanently assigned on the device. If spare SLC-type memory block eventually go had or become unusable, the capacity of the SLC-type storage region cannot be adjusted and the device cannot be updated any further. Furthermore, these file management systems are typically stored external to the device, such as in software stored in the processor or memory controller. In order to correctly access the various regions of the MLC memory, each block of memory must include individual markers, headers, and block attribute data in some cases, each page or sector of the memory block must allocate space to store tag bits and other identifiers that can be tracked by the file management system. The file management system then has the burden of tracking a plethora of markers, identifiers and block attribute information throughout the device. Consequently, prior art multi-mode MLC memory systems are prone to errors, misplaced data, and delays when responding to data requests or writes.
Therefore, there is a need for a memory system with the ability to store both less reliable data and high reliability data on the same device, and a need to dynamically manage memory partitions at a centralized location.